1. Field of the Invention
The present invention relates to a digital image processing apparatus for performing operation processing of original image data, to execute image data conversion processing such as correction of gradation or increase of sharpness of the image and other processing such as feature extraction from the original image data.
2. Description of the Prior Art
FIG. 1 is a block diagram showing an example of a conventional digital image processing apparatus. This conventional digital image processing apparatus comprises a host central processing unit (CPU) 1, an image input circuit 2, an image memory 3, an operation processing circuit 4, an image output circuit 5, a host CPU bus L1 and an image data bus L2. Pluralities of image input circuits 2, image memories 3, operation processing circuits 4 and image output circuits 5 may be provided as required. This image processing apparatus performs three fundamental functions, i.e. image data input processing, image data operation processing and image data output processing.
(1) Image data input processing is performed by writing image data applied from the image input circuit 2 into the image memory 3 through the image data bus L2.
(2) Image data operation processing is performed in a manner in which the image data read out from the image memory 3 is inputted to the operation processing circuit 4 through the image data bus L2 to be subjected to operation processing and the data obtained therefrom is written in the image memory 3 through the image data bus L2.
(3) Image data output processing is performed in a manner in which the image data read out from the image memory 3 is supplied to the image output circuit 5 through the image data bus L2 and outputted to an external apparatus such as an image display or an image recorder.
According to the respective functions, the image input circuit 2, the image memory 3, the operation processing circuit 4 and the image output circuit 5 need to have prescribed input and output relations with the image data bus L2 and need to be set to prescribed operation conditions. More specifically, in order to perform a desired image processing function, it is necessary to set those circuits included in a hardware portion to prescribed operation conditions. In addition, in order to perform different image processing functions successively, it is necessary to renew setting of operation conditions successively.
In the conventional apparatus in FIG. 1, such setting of operation conditions is effected in software processing of the host CPU 1 by allotting I/O areas of the host CPU 1 for condition setting of the hardware to be controlled. In this case, all of the control operations, including control of desired image processing based on algorithm and setting of detailed conditions of the hardware, depend on the software processing of the host CPU 1. Consequently, the proportion of the whole area of the image processing software of the host CPU 1 assigned for control of the hardware becomes large and accordingly, the software area is increased. Thus, there is a large dependency of the software on the hardware. In addition, it is difficult to achieve high-speed control of the hardware since it is necessary to fetch a program for control of the hardware.
In order to solve the above described problems, digital image processing apparatuses as described below have been proposed. More specifically, in one of such digital image processing apparatuses, a control circuit for controlling a hardware portion is provided between the host CPU having control of software processing and the hardware portion performing actual image processing. A microprogram concerning control information for the respective circuits of the hardware portion is stored in a microprogram memory provided in the control circuit. Thus, if the microprogram is read out from the microprogram memory in response to a processing request of the host CPU, necessary control of the hardware portion is performed in the control circuit to execute a prescribed image processing function. FIG. 2A is a block diagram showing another conventional example of the above mentioned proposed digital image processing apparatuses. Referring to FIG. 2A, a control circuit 6 is provided between the host CPU bus L1 and the hardware circuits 2 to 5 to be controlled. The control circuit 6 interprets a control request from the host CPU 1 and provides control signals corresponding to the respective hardware circuits 2 to 5.
FIG. 2B shows an internal construction of the control circuit 6 shown in FIG. 2A. The control circuit 6 comprises a command decoder 601, a microprogram memory read control circuit 602, a microprogram memory 603 and a microprogram decoder 604. The host CPU 1 does not perform control operations for the respective hardware circuits and supplies codes to the command decoder 601 according to contents of processing. The command decoder 601 decodes the supplied codes and operates the microprogram memory read control circuit 602 according to the decoded contents. The microprogram memory read control circuit 602 is brought into two states, i.e. a stop state and a state in which an address for reading of the microprogram memory 603 is provided. Commands provided from the command decoder 601 represent in principle requests for selecting either of the two states, i.e. a request for beginning to read the microprogram memory 603 and a request for stopping of the reading.
The microprogram memory 603 receives a read address, a read permission signal and the like from the microprogram memory read control circuit 602 and reads the microprogram. The thus read microprogram is supplied to the microprogram decoder 604. The microprogram decoder 604 decodes the supplied microprogram and generates a control signal in a form necessary for the hardware circuits.
According to the above described control system, the proportion assigned for hardware control in the software of the host CPU 1 is considerably decreased and the software depends less on the hardware. In addition, the hardware portion can be controlled at higher speed.
Thus, the control information for the hardware portion is microprogrammed, which makes it possible to decrease the workload of the host CPU 1 and to perform processing at high speed. However, the conventional apparatus shown in FIGS. 2A and 2B involves a disadvantage that design of the controlled hardware circuits 2 to 5 has little flexibility. More specifically, if a modification is made or a new component is added in one of the controlled hardware circuits 2 to 5, it is necessary to change the circuit configuration of the microprogram decoder 604 according to such modification o addition and it is also necessary to change or add control signal lines between the control circuit 6 and the controlled hardware circuits 2 to 5, which is troublesome. Thus, it is considerably difficult to add a new circuit to the hardware circuits or to change the hardware circuits.
In addition, such a conventional microprogrammed control system of a digital image processing apparatus has a problem that a loss in time for control of the hardware portion is caused because there is no means for synchronization between operation timing of the hardware portion concerning, for example, a period for reading image data of a pixel or a frame from an image memory and timing for control of reading of a microprogram from a microprogram memory, decoding of the microprogram by the microprogram decoder or the like. For example, in a system in which access to an image memory is effected by raster scanning of a prescribed cycle and all the other hardware circuits operate dependent on the prescribed cycle, if no synchronization is effected between timing for control operation and the cycle of raster scanning, a period corresponding to one cycle or two cycles of raster scanning is required only for the control operation even if the period actually for the control is very short.
In addition, in the conventional apparatus shown in FIGS. 2A and 2B, the microprogram in the microprogram memory 603 is formed simply by programming, as microinstructions, a sequence of control instructions for the controlled hardware circuits 2 to 5, and processing related to the algorithms of image processing, such as combination of different microprograms or repetitive execution of the same microprogram, is performed by software processing of the host CPU 1. Thus, software processing by the host CPU 1 occurs during a plural number of microprogram reading operations, causing a delay in control operation for the controlled hardware circuits 2 to 5. In order to decrease the number of occurrences of software processing, it is necessary to combine, as required, a plurality of microprograms existing independently in the microprogram memory 603 or to utilize the same microprogram for a plural number of times. For doing so, it is necessary to provide not only the control instructions for the hardware circuits 2 to 5, but also microinstructions for reading control of the microprogram, such as jumping instructions, condition determining instructions, subroutine call instructions or return instructions from the subroutines, indispensable for software processing, and it is also necessary to make the microprogram decoder in the control circuit have a function of decoding those reading control microinstructions.